Approaches to defect characterization, mitigation and reduction

Ever since its inception in the late 1980s, chemical-mechanical planarization (CMP) has been the pivotal enabling process in the manufacturing of integrated circuits (IC). Whether it is for front-end-of-the-line (FEOL) applications such as shallow trench isolation (STI) and metal gate, or back-end-of-the-line (BEOL) such as Cu interconnects or through-silicon via (TSV), CMP is the terminal step that completes a process module. As a consequence, the defects observed after CMP have direct impacts on the yield and reliability of the devices and circuits. Provided the nature of CMP process described above and its heavy usage of consumables, CMP-related defects are complicated in nature. Not only does CMP generate defects from its own process and consumables involved, but it also reveals the defects not detected and removed from all the up-stream process steps. In addition, the tolerance and specification for post CMP defect density will only become more stringent as the device dimension continues to decrease with shrinking design ground rule. For example, in the 7 nm technology node, the width of Cu interconnects in the thin wire levels is only around 24 nm, which is smaller than the diameter of abrasive nano particles in most CMP slurries. The presence of any post-CMP defects of equal or greater size on the Cu surface poses serious concern for yield loss. As a consequence, the characterization, mitigation, and reduction of CMP-related defects are among the most important yet challenging tasks in IC manufacturing. In this chapter, CMP defects will be categorized by their formation mechanism. The roles of consumables and processes in the generation of CMP defects will be discussed. The characterization of defects and the strategies to mitigate and reduce these defects will be elaborated. The chapter will be organized according to the following index: