SRAM technology status and perspectives

Static Random-Access Memory (SRAM) is one of the fundamental components of modern System-on-Chips (SoCs). CMOS technology scaling increases SRAM density and performance. The larger and faster on-die cache has improved the performance of microprocessors over the last few decades. Transistor sizing (known as cell sizing) is historically employed in SRAM to the trade-off between cell area, noise immunity, write ability, speed, leakage power, and dynamic power. However, the transition from the planar device to FinFET makes the cell sizing difficult due to fin quantization. SRAM area scaling is saturating due to the difficulty in fin pitch and metal pitch scaling. Furthermore, in most advanced nodes, interconnect resistance (bitline and wordline), as well as random variations, are increased significantly. Increased interconnect resistance degrades SRAM performance while increased random variations lead to a larger minimum operating voltage (Vmin). This book chapter summarizes recent research activities to circumvent SRAM design challenges in most advanced technology nodes.