A study of failure mechanism in the formation of fine RDL patterns and Vias for heterogeneous packages in chip last fan-out panel level packaging

The heterogeneous integration including multiple die packaging, passive component has been developing for a range of applications. Fan-out technology is a way to assemble one or more dies in an advanced package, enabling chips with better performance for applications such as HPC, IoT, networking and smartphones. In fan-out, the RDL traces can be routed inward and outward, enabling thinner packages with more I/Os. In this paper, the design rule of L/S 2/2um with interconnect length more than 6 mm was adopted to 2.5D chip last Test vehicle for 1 ASIC and 1 HBM interconnection to demonstrate the level of mass production in panel level HVM line. During the evaluations, a number of open/short failures of 4 um-pitch patterns and via dimple defect were observed. To solve these problems, undulation underneath the fine pitch RDL was reduced to less than 2 um by changing the UBM structure and exposure dose was optimized to remove the bottom of the small via. As a results, the yield was enhanced dramatically.