Novel method of wafer-level and package-level process simulation for warpage optimization of 2.5D TSV

2.5D IC packages are typically produced through Chip on Wafer (CoW) or Chip on Substrate (CoS) processes. Among these, 2.5D processing involves bonding the interposer chip and ASIC chip perpendicularly in sequence to the substrate for 2.5D package production. However, due to the large size of the interposer chip and its commensurately large high temperature warpage, attaching the interposer chip to the substrate carries a high risk of interconnection defects (non-wet/short) at the chip-substrate joints arising from the warpage difference. Moreover, the warpage difference between the attached interposer chip and ASIC also leads to a high risk of interconnection defects during bonding. For this reason, accurate prediction of the interposer chip high temperature warpage is of utmost importance in 2.5D packages In package warpage simulation, the reference (stress free) temperature is generally taken from high-T processes such as molding or F/C mounting, as they are most critical in inducing package warpage. However, unlike an IC package, the interposer chip undergoes no dominant process in particular which is critical to its chip warpage. Instead, all device fabrication processes prior to package formation impact the final interposer chip warpage. The initial room temperature warpage is determined by the residual stress from each processing step. The high temperature warpage is determined by the difference in metal density between the regions above and beneath the silicon as the temperature is increased. In the present study, we examine a 28.3×18.9 mm 4-layer BEOL, 1-layer B-RDL interposer chip in order to predict the final interposer chip warpage via the finite element method (FEM) and thereby more effectively control it. To that end, we obtain the residual stress resulting from the front side (BEOL) and back side (B-RDL) processes through warpage measurement at each step. Moreover, we propose a method to maintain the interposer chip warpage close to zero, by adjusting the metal density and CVD film properties. In addition, we aim to address and improve possible Joint defects (non-wet/short) during ASIC chip bonding by predicting the warpage of the interposer chip attached to the substrate.