Failure Analysis of Nano-Tsv Process Flow

In this paper, the process flow of copper (Cu) filled Nano Through Silicon Via (Nano-TSV) with aluminum (Al) Frontside Metal (FSM) and Backside Metal (BSM) fabricated using Silicon-On-Insulator (SOI) wafer is introduced, which is a key enabler to realizing the Backside Power Delivery Network (BSPDN). Electrical tests were conducted on test structures distributed across the entire wafer. Combined analysis of the electrical data and Focused Ion Beam Transmission Electron Microscopy (FIB-TEM) imaging enables identification of the root causes of failure. It is found that nonuniformity in metal layer processing, along with deficiencies in Nano-TSV etching and filling, are the primary contributors. Hypotheses of failure mechanisms for Nano-TSV filling are discussed, and subsequent process optimizations led to successful results, as confirmed by FIB-TEM imaging.