Degradation Analysis of SiC MOSFETs Under High Temperature Gate Bias Stress Above 200°C

This study addresses the reliability challenges of ceramic-packaged silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) under long-term high-temperature gate bias (HTGB) stress exceeding 200 °C.We systematically analyzed the degradation patterns and mechanisms of devices under HTGB stress through the characterization of key electrical parameters. HTGB was performed under a +30 V gate bias at 220 °C for 1000 hours, accompanied by periodic static parameter characterization, with particular focus on the evolution of threshold voltage (Vth). Experimental results indicate a progressive increase in on-resistance (Ron), reflected in downward-shifting output characteristics, while Vth exhibits a positive drift with aging time. This behavior is primarily attributed to charge trapping at interface traps and near-interface oxide traps. The analysis reveals that long-term positive gate bias-induced electron accumulation serves as the primary mechanism responsible for Vth variation. These results yield vital empirical insights regarding SiC power MOSFET reliability at elevated temperatures. This demonstrates that ceramic packaging substantially enhances thermal endurance and emphasizes that effective control of interface charge trapping is crucial for mitigating parameter degradation.