An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input-Buffer-Sampling Scheme and Fast Robust Background Inter-Stage Gain Calibration

High-resolution ADCs operating at medium speed (1-20MS/s) can be effectively realized utilizing the energy-efficient pipelined-SAR architecture [1]–[2]. However, a large sampling capacitance is required to suppress the thermal noise, making ADCs challenging to drive. Although the integrated driving techniques have been explored, they still require either a higher supply [3]–[6] or a predictor [7]–[8], limiting its application scenarios. Another factor that may limit the energy efficiency is the residue amplifier, which costs substantial power to achieve a sufficient bandwidth for settling. The use of an energy-efficient dynamic amplifier can address this problem [9]–[11], but it often suffers from inter-stage gain variation under PVT conditions, necessitating background calibration [12]–[17]. This calibration must be fast, robust and capable of working under different input conditions. This work presents an easy-drive 16MS/s pipelined-SAR ADC using the split coarse-fine input buffer sampling scheme. Additionally, a fast and PVT-robust background inter-stage gain calibration is proposed using offset cancellation and metastability detector with probability control. To ensure convergence across different input conditions, a 2b input dither is injected. The prototype ADC achieves 79.4dB SNDR and 99.4dB SFDR at Nyquist input with 1.8/0.9V supply, and is capable of processing $\text{rail}-\text{to}-\text{rail}\ 3.6\mathrm{V}_{\text{ppd}}$ input with the integrated input buffer.