随时间变化的栅氧化层击穿
栅氧化层
材料科学
介电强度
击穿电压
可靠性(半导体)
光电子学
MOSFET
薄脆饼
氧化物
阈值电压
功率MOSFET
CMOS芯片
沟槽
电子工程
电气工程
电压
电介质
功率(物理)
工程类
纳米技术
晶体管
图层(电子)
物理
冶金
量子力学
作者
T.E. Kopley,Matt Ring,Chang Min Choi,J. Colbath
标识
DOI:10.1109/iirw.2015.7437087
摘要
We present a gate oxide breakdown analysis method that uses an effective oxide thickness model combined with Time-Dependent Dielectric Breakdown (TDDB) model parameters to assess the reliability of extrinsic gate oxide defects. The method transforms gate breakdown voltage (Vbd), obtained from voltage ramp-to-breakdown measurements, into effective oxide thickness (teff) and compares these to the minimum oxide thickness that gives 10 or 20 years TDDB lifetimes. The analysis allows binning of extrinsic defects (Jedec mode B) into reliable and unreliable populations. It also gives an optimal gate screen voltage that can be used at wafer sort to screen parts with unreliable gate oxides. This method is valid for any CMOS process, but is especially useful for BCDMOS and Power Trench MOSFET technologies that use very large devices and ship in large volumes.
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