Throughput optimization by pipeline alignment of a Self Synchronous FPGA

We report on the throughput optimization of a self synchronous FPGA (SSFPGA) using benchmark circuits. We find that using a dual pipeline architecture we are able to convert synchronous designs from verilog onto our SSFPGA, and by using pipeline alignment techniques to match pipeline depth we can perform at maximum throughput. We demonstrate 0 to 56.1 times throughput improvement with our pipeline alignment techniques. The pipeline alignment is carried out within the number of logic elements in the array and pipeline buffers in the switching matrix.