Junction Engineering-Based Modeling and Optimization of Deep Junction Silicon Single-Photon Avalanche Diodes for Device Scaling

A silicon single-photon avalanche diode (Si-SPAD) with a deep multiplication zone was fabricated using 0.11- $\mu \text{m}$ -CMOS technology. Deep n-well (DNW) implantation with three energy levels was performed to prepare a deep junction, and the highest breakdown voltage ( ${V}_{\text {BR}}$ ) and lowest dark count rate (DCR) were obtained at the highest DNW implantation energy. In addition, devices with different structures were manufactured: a shallow junction, deep junction with mask DNW, deep junction with mask DNW without shallow trench isolation (STI), and deep junction with blank DNW. The blank DNW structure exhibited a lower edge breakdown risk and less deviation between samples compared to those of mask DNW structure in terms of the ${V}_{\text {BR}}$ and DCR. Moreover, a new edge breakdown risk was observed between DNW and p-well (PW) in the DNW blank structure, which could be alleviated by adjusting the PW sizes. According to the measurement results, the STI structure was preferable in terms of fill factor. Measurements were obtained from real fabricated test device structures, and technology computer-aided design (TCAD) for various factors associated with Si-SPADs with deep multiplication structures was performed.