A low power external capacitor‐less low drop‐out regulator with low over/undershoot voltage and high PSR

Summary This paper presents a new architecture for improving power supply rejection (PSR) and load transient response in a capacitor‐less low drop‐out (LDO) voltage regulator. In the proposed architecture, inserting a leading path from the power supply to the gate of the pass transistor keeps the pass transistor gate‐source voltage constant in the presence of the supply voltage ripples that results in the PSR enhancement of the LDO. In addition, by using a frequency compensation technique, the amount of undershoot and overshoot voltages in the presence of a sudden change of load current are reduced. Because of the creation of a zero in the LDO's transfer function, the effect of non‐dominant pole on the phase of LDO is reduced, and a 58° phase margin is achieved without any off‐chip capacitor. As reducing the power consumption as much as possible increases the battery life, therefore, in addition to using the current‐reused technique, the transistors of control circuit are biased in the subthreshold region. The proposed regulator with a total of only 3.1 pF on‐chip capacitor is designed and simulated in 180 nm complementary metal‐oxide semiconductor (CMOS) technology for an output regulated voltage of 1.6 V and a load current of 50 μA to 50 mA. Post‐layout simulation results show that the proposed circuit with an active area of 0.0145 mm 2 and the input voltage of 1.8 to 2.4 V has only 1.504 μW power dissipation and −80 and −64 dB PSR at 1 and 10 kHz frequencies, respectively.