PI/SI Analysis and Design Approach for HPC Platform Applications

In this work, we introduce a comprehensive methodology for the power integrity/signal integrity analysis of SoC and silicon-based interposers in a HPC platform. By conducting a comprehensive investigation of the global chip-level PDN impact by electrical interactions between the chip, package, and board in the system, an efficient power delivery network was designed to meet HPC specifications. This was achieved by extracting long-term test scenarios (microsecond-order duration) to estimate voltage drop at the bumps and deployment of decoupling capacitors considering the optimal placement and numbers within an allowable cost budget. This analysis also yielded the benefit of reduction in power domains/ball count/package layers which further reduced costs. In addition to the Power Integrity, signal properties were analyzed under the allowed channel conditions (channel width and spacing, shielding lane placement). As a result, the channel design parameters are found to meet the criteria of eye opening including power noise and crosstalk effects. It was demonstrated that the electrical properties of the HBM2e IP are successfully operational up to 3.2Gbps.