A High-PSRR NMOS LDO Regulator With Intrinsic Gain-Tracking Ripple Cancellation Technique

This paper presents an NMOS low dropout (LDO) regulator with a high-power supply rejection ratio (PSRR) and low quiescent current that uses an intrinsic gain-tracking ripple cancellation (IGTRC) technique with an adaptive biasing scheme. The proposed LDO is fabricated using a 180 nm CMOS process and achieves a quiescent current of $3.7~\mu $ A with superior figure-of-merits (FOMs) of 7.6E9 (FOM1) and 0.005 ps (FOM2).