Insights Into Parasitic Capacitance and Reconfigurable FET Architecture for Enhancing Analog/RF Metrics

Through an insightful analysis of different architectures of reconfigurable field-effect transistor (FET) (RFET), the work showcases its potential to achieve improved voltage gain ( ${A}_{V}$ ), cutoff frequency ( ${f}_{T}$ ), and gain–bandwidth product ( ${A}_{V} \times {f}_{T}$ ) at low current levels. The extraction of parasitic components reveals lower total parasitic capacitance ( ${C}_{\text {parasitic}}$ ) in RFET as compared to a double gate (DG) MOSFET for the same total length ( ${L}_{\text {T}}$ ) despite a greater number of gates. While a twin-gate RFET architecture is more suitable for high-gain applications, a three-gate RFET topology is more favorable for larger bandwidth. The flexibility to optimize control gate (CG) length ( ${L}_{\text {CG}}$ ), ungated length ( ${L}_{\text {UG}}$ ), and polarity gate (PG) length ( ${L}_{\text {PG}}$ ) for the same ${L}_{\text {T}}$ can be best utilized through a three-gate RFET with ${L}_{\text {CG}}/{L}_{\text {T}} \ge0.4$ and ${L}_{\text {UG}}/{L}_{\text {T}}$ = 0.1 to attain high values of both ${f}_{\text {T}}$ and ${A}_{\text {V}}$ as compared to MOSFET. Results provide new viewpoints for optimizing analog/RF metrics at low current levels through twin-gate and three-gate RFETs.