Exploring Efficient Thermal Management Solutions for Backside Power Delivery Network (BSPDN) Systems Using Multiscale Modeling

The backside power delivery network (BSPDN) is seen as a transformative technology for the next generation of chip designs. However, it introduces significant thermal challenges compared to the conventional frontside power delivery network (FSPDN). Modeling analysis of CPU hotspot areas indicates that BSPDN results in temperatures approximately 45% higher than FSPDN. To address these thermal challenges, we have systematically explored both conduction and convection cooling solutions. These include the use of advanced bonding interfaces with thermal conductivity [ranging from 0.2 to 1000 W/(m $\cdot $ K)], various back end of line (BEOL) layer configurations (stacked, staggered, and isolated), advanced BEOL metal materials (such as Cu, Ru, and Co interconnects), and embedded microchannel cooling within the backside metal (BSM) region to effectively dissipate heat toward the bottom substrate. The microchannel design is inspired by the geometric similarities between the airgap-BEOL structure and cutting-edge 3-D manifold microchannel coolers. To address the modeling challenges posed by the multiscale (ranging from 20 nm to $100~\mu $ m) and multiphysics (thermal and fluid dynamics) simulations within the BSPDN system, we have adopted an integrated modeling framework proposed by IMEC. This framework serves as a research tool to support our in-depth thermal solution exploration and analysis. For studying the effective BEOL properties, a small-scale model of $1\times 1~\mu\mathrm{m}^{2}$ is used to extract the equivalent thermal conductivity of an eight-layer Mint-M8 BEOL, which is then applied for thermal analysis under different BEOL interconnect configurations. A $0.12\times 0.12~\mu\mathrm{m}^{2}$ model containing Mint-M3 is employed for material matrix studies. For hotspot analysis, a larger $10\times 25~\mu\mathrm{m}^{2}$ model is used to generate temperature distribution maps with various heat-spreading materials and embedded microchannel cooling parameter investigations. These proposed solutions are expected to significantly enhance the thermal performance of BSPDN. Ultimately, this article aims to provide a comprehensive set of thermal design guidelines for the BSPDN architecture, advancing chip power, performance, and area (PPA) in advanced technology nodes.