Patterning challenges of EUV lithography for 1X-nm node DRAM and beyond

In this paper, we will discuss patterning challenges of EUV lithography to apply 1xnm node DRAM. EUV lithography is positioned on essential stage because development stage for DRAM is going down sub-20nm technology node. It is time to decide how to make sub-20nm node DRAM. It will be the simplest and cost effective way to make device with matured EUVL. But in spite of world-wide effort to develop EUV lithography, the maturity of EUV technology is still lower than conventional ArF immersion lithography. So, DRAM manufacturers are considering several candidates such as DSA, DPT and MPT simultaneously. In addition, DRAM manufacturers are considering new cell layout and new memory also. For this study, we investigate process window and shadow effect across exposure field of sub-20nm node DRAM cell. We also performed an overlay matching experiment between 0.25NA EUV scanner and 1.35NA ArF immersion scanner. In addition, we will compare EUV lithography with ArF immersion DPT or SPT in view of patterning performance. Finally, we will discuss some technical issues to applying EUV lithography such as flare, resist LER, EUV OPC and illumination condition using 0.25NA EUV scanner.