An Ultralow Power System on Chip for Automatic Sleep Staging

This paper presents an ultralow power system on chip (SoC) for automatic sleep staging using a single electroencephalogram (EEG) channel. The system integrates an analog front end for EEG data acquisition and a digital processor to extract spectral features from these data and classify them into one of the sleep stages. The digital processor consists of multiple blocks implementing an automatic sleep staging algorithm that uses a set of contextual decision trees controlled by a state machine. The processor is designed to stay in the idle mode at most times waking up only when computations are required. In addition, the mathematical operations are implemented in a way such that the number of datapath components needed is very small. The SoC is implemented in an AMS 0.18-μm CMOS technology and is powered using a single 1.25-V supply. Its power consumption is measured to be 575 μW, while its classification accuracy using real EEG data is 98.7%.