可制造性设计
化学机械平面化
设计流量
平版印刷术
标准电池
过程(计算)
模具(集成电路)
计算机科学
进程窗口
炸薯条
物理设计
集成电路设计
节点(物理)
集成电路
材料科学
工程类
嵌入式系统
电路设计
机械工程
电气工程
电信
抛光
操作系统
结构工程
光电子学
作者
Xiaojing Su,Yayi Wei,Rui Chen,Yajuan Su,Lisong Dong,J.W. Kwan,Recoo Zhang,Chunshan Du,Qijian Wan,Xinyi Hu
摘要
Design technology co-optimization (DTCO) is one of the most critical considerations for yield breakthrough and product ramp-up during the life cycle of a new technology node. Traditional sign-off flow of physical verification cannot guarantee manufacturability totally. Comprehensive design for manufacturing (DFM) check should be involved in flow of product tape-out in order to recognize the patterning and other process challenges which would limit the wafer yield. The process related hotspots were pre-defined with the aid of process related simulation kits on cell, block as well as full chip levels. A systematic DTCO methodology including fabless process friendly flow with lithography friendly design (LFD), pattern match and chemical mechanical planarization (CMP) check, resolution enhancement technology (RET) synthesis, process window check for sensitive patterns as well as weak pattern library assisted circuit diagnosis was as an example of DTCO application at 14/12nm in this paper.
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