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Accumulation-Mode Device: Experimental of LDMOS With Folded Drift Region Achieving Ultralow Specific ON Resistance

LDMOS 击穿电压 电场 电极 电子 兴奋剂 材料科学 电气工程 物理 拓扑(电路) 光电子学 凝聚态物理 电压 量子力学 工程类
作者
Baoxing Duan,Ziyu Zhou,Yandong Wang,Yintang Yang
出处
期刊:IEEE Transactions on Electron Devices [Institute of Electrical and Electronics Engineers]
卷期号:69 (10): 5728-5732 被引量:5
标识
DOI:10.1109/ted.2022.3200628
摘要

In order to reduce the specific ON resistance ( $\text{R}_{\mathbf {{ \mathrm{\scriptscriptstyle ON}},sp}}$ ) of power device in the drift region, the folded accumulation lateral double-diffused MOSFET (FALDMOS) is manufactured and analyzed in this article. The drift region of the FALDMOS is etched to form the folded surface, which is similar to the FinFET structure. The oxide inside the trench optimizes the electric field in the drift region, so the doping concentration can be increased while maintaining the breakdown voltage (BV). In addition, the trench increases the area of the drift region covered by the extended gate electrode, which can introduce more accumulated electrons when the device is turned on. The increased doping concentration and accumulated electrons work together to substantially increase the conductivity of the drift region, thereby obtaining ultralow $\text{R}_{ \mathrm{\scriptscriptstyle ON},sp}$ . Furthermore, the folded accumulation LDMOS with split gate (FSLDMOS) is proposed to solve the phenomenon that the BV of the FALDMOS cannot be improved by increasing the drift length with the fixed oxide thickness. The polysilicon above the drift region is etched apart to form an extended gate and a split electrode. The electric field concentration near the drain can be alleviated by adjusting the bias on the split electrode. The FALDMOS and FSLDMOS are manufactured by the 0.35- $\mu \text{m}$ BCD technology and the key processes, such as trench etching and polysilicon filling, are shown. The experimental results show that $\text{R}_{ \mathrm{\scriptscriptstyle ON},sp}$ of the FALDMOS is only 9.3 $\text{m}\Omega \cdot $ mm2, while that the conventional LDMOS is 36.2 $\text{m}\Omega \cdot $ mm2, which is reduced by 74.3% with the same BV of 36 V. Moreover, the current density of FALDMOS is five times higher than that of the conventional LDMOS in the same areas. The BV of the FSLDMOS is improved by 66% compared with FALDMOS.
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