An Adaptive Three-Stage GaN Gate Driver With Peak Miller Plateau Voltage Tracking and Voltage Tailing Suppression for 36.4% Switching Loss Reduction

Achieving low switching loss is critical for high-frequency gallium nitride (GaN)-based power converters due to the compact packaging and limited heat dissipation capacity of GaN devices. Focusing on minimizing the switching loss, this article proposes an adaptive three-stage gate driver (ATSGD) for GaN high electron mobility transistor (GaN HEMT). By providing a three-stage driving current within the Miller plateau (MP) stage, the proposed ATSGD can achieve a near-constant dV/dt, thus minimizing the switching loss under specific peak dV/dt constraints. Utilizing peak MP voltage tracking (PMPVT) and quick voltage tailing suppression (QVTS) techniques, the driver dynamically determines optimal switching timings for the three-stage driving currents in real time. Therefore, the extra losses caused by slow dV/dt start-up and voltage tailing effect are minimized under dynamic operation conditions. Fabricated in a $0.18~{\mu }$ m bipolar-CMOS-double-diffused metal oxide semiconductor (BCD) process, the proposed driver reduces the total switching loss by 36.4% under 400 V/15 A with a peak dV/dt of 45 V/ns, benefiting from a 46.1% reduction in slow dV/dt start-up loss and an 88.7% reduction in voltage tailing loss compared with conventional gate drivers.