神经形态工程学
冯·诺依曼建筑
计算机科学
瓶颈
CMOS芯片
矩阵乘法
非常规计算
计算机体系结构
记忆电阻器
并行计算
计算机工程
电子工程
人工智能
分布式计算
人工神经网络
嵌入式系统
工程类
物理
量子力学
量子
操作系统
作者
Navnidhi K. Upadhyay,Hao Jiang,Zhongrui Wang,Shiva Asapu,Qiangfei Xia,J. Joshua Yang
标识
DOI:10.1002/admt.201800589
摘要
Abstract A neuromorphic computing system may be able to learn and perform a task on its own by interacting with its surroundings. Combining such a chip with complementary metal–oxide–semiconductor (CMOS)‐based processors can potentially solve a variety of problems being faced by today's artificial intelligence (AI) systems. Although various architectures purely based on CMOS are designed to maximize the computing efficiency of AI‐based applications, the most fundamental operations including matrix multiplication and convolution heavily rely on the CMOS‐based multiply–accumulate units which are ultimately limited by the von Neumann bottleneck. Fortunately, many emerging memory devices can naturally perform vector matrix multiplication directly utilizing Ohm's law and Kirchhoff's law when an array of such devices is employed in a cross‐bar architecture. With certain dynamics, these devices can also be used either as synapses or neurons in a neuromorphic computing system. This paper discusses various emerging nanoscale electronic devices that can potentially reshape the computing paradigm in the near future.
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