纳米线
材料科学
结晶
光电子学
纳米技术
电气工程
物理
热力学
工程类
作者
Chih-Chao Yang,Wei‐Hsiang Huang,Teh-Sheng Hsieh,Tsung‐Ta Wu,Hsing-Hsiang Wang,Chang‐Hong Shen,Wen‐Kuan Yeh,Jung-Hau Shiu,Yu‐Hsiu Chen,Meng‐Chyi Wu,Jia‐Min Shieh
标识
DOI:10.1109/led.2016.2537381
摘要
Three-dimensional sequentially stackable high- $k$ /metal-gate-stacked tri-gate nanowire poly-Si FETs with embedded source/drain (e-S/D) and back gate were demonstrated. The highly crystallized channel, fabricated by green nanosecond laser crystallization, chemical mechanical polish, and postsurface modification processes, enhances the electrical property of the tri-gate nanowire FET. The e-S/D structure reduces the contact and series resistances caused by the nanowire structure. Thus, the fabricated n/p-type tri-gate nanowire poly-Si FETs exhibit steep subthreshold swings (96/125 mV/decade), high ON-currents (232/110 $\mu \text{A}/\mu \text{m}$ ), and $I_{{\mathrm{\scriptscriptstyle {on}}}}/I_{\mathrm{\scriptscriptstyle {OFF}}}$ ratio ( $> 10^{5})$ . Furthermore, the independent back gate with thin back gate oxide can easily adjust the threshold voltage of the tri-gate nanowire transistor and results in high gamma value (>0.05) FET realizing sequentially stacked and low $V_{\mathrm {dd}}$ (0.6 V) operable inverter.
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