Investigation of improving the uniformity of Cu dishing depth in Cu-SiO2 chemical mechanical polishing

As chip manufacturing trends towards miniaturization and integration, the focus of the semiconductor industry has shifted from traditional 2D packaging to more complex 3D packaging, with hybrid bonding technology emerging as a critical method for heterogeneous integration. Currently, Cu-Cu/SiO2-SiO2bonding is the mainstream hybrid bonding technique. To achieve effective bonding, wafers require surface planarization of Cu-SiO2through chemical mechanical polishing (CMP). The CMP process for Cu-SiO2surfaces typically consists of two steps: copper CMP and barrier layer CMP. However, due to the uneven thickness of electroplated copper, over-polishing is inevitable during the copper CMP in order to effectively remove the copper layer. This will lead to excessive dishing or recession of Cu pads with orginal thinner Cu layer electroplated and then finally affect the bonding quality. To address this challenge, in this paper, a three-step CMP method is developed, which introduces an additional SiO2CMP step after the barrier layer CMP to achieve the appropriate dishing depth of the pads. In this study, the influence of pad size on the Cu pad dishing depth was investigated. The results indicated that as the polishing time increased, the Cu pad dishing became deeper and larger pad sizes resulted in a faster growth rate of the dishing depth. The polishing slurry plays an important role in the CMP process. It is necessary to find a polishing slurry with appropriate material remove rate during additional SiO2CMP to reduce the Cu dishing. Through experiments, a SiO2polishing slurry was selected with Cu: SiO2remove rate of 1:3. Then the process parameters for the SiO2CMP were optimized to achieve an ideal dishing depth for the pads. Finally, the dishing depth of pads with a side length of 15um was optimized from 100~200nm to 20~40nm. The experimental results indicate that this method can correct the Cu dishing caused by over-polishing even for large pads, eliminate the negative impact of dishing on subsequent bonding processes, and decrease the requirement for flatness of electroplated Cu on wafer.