Cost-effective, high-performance heterogeneous integration for 6.4T and beyond 224Gbps/lane co-packaged-optical engines for AI/ML and data center

Heterogeneous integration (HI) is a highly promising approach to integrate photonic and electronic chips to form optical engines (OE) which address the crucial I/O bottleneck in hyperscale Data Centre (DC) switches and AI/ML clusters in high performance computing (HPC). Cost, performance, and manufacturability are key challenges for HI. In this paper we present the design, process-integration, test-results for a novel Fan-out Wafer Level Package (FOWLP) approach to realize cost-effective, volume-manufacturable, high-performance OEs for 1.6T/6.4T and beyond.