0.35μm CMOS Technology with Chemical Mechanical Polishing for Three Metallization Levels Planarization

Multilevel metallization is a key process for the technology generations below 0.5μm. As the design rules are going smaller, the limits of the classical SOG Etch-Back process are reached in terms of process complexity and long distance planarization. The solution to this problem is to use a Chemical Mechanical Polishing technique for the dielectric planarization. In this paper, we will demonstrate that this CMP technique is compatible with a 0.35 CMOS technology in terms of transistor behaviour and triple metal process assembly.