A Command-Aware Hybrid LDO With Ultra-Small Voltage Droop and Fast Settling Time for Power-Supply-Induced Jitter Mitigation in HBM Interfaces

This work presents a command-aware hybrid low-dropout regulator (CA-HLDO) designed to mitigate voltage droop and power-supply-induced jitter (PSIJ) in write DQS (WDQS) buffers for high-bandwidth memory (HBM) interfaces. In HBM standards, WDQS buffers experience abrupt load current ( $I_{\mathrm {L}}$ ) transitions, leading to significant voltage droop in the environment of the complexity of the power delivery network (PDN). However, conventional analog LDOs (ALDOs) and event-driven LDOs (ED-LDOs) suffer from a limited loop bandwidth, making it difficult to prevent large voltage droops and PSIJ degradation. To address these challenges, the proposed CA-HLDO leverages a unique property of memory systems: the magnitude and timing of $I_{\mathrm {L}}$ are deterministic based on commands from the host. Exploiting this property, the CA-HLDO proactively sources a current ( $I_{\mathrm {D}}$ ) that matches $I_{\mathrm {L}}$ precisely at the time of its occurrence, thereby minimizing voltage droop and reducing the settling time ( $T_{\mathrm {S}}$ ). The architecture includes an $I_{\mathrm {D}}$ adaptor to dynamically adjust the magnitude of $I_{\mathrm {D}}$ and a control signal generator (CSG) to calibrate the timing of $I_{\mathrm {D}}$ sourcing. Fabricated in a 40-nm CMOS, the CA-HLDO achieved sub-10-mV voltage droop and 400-ps settling time using a small output capacitor and minimal quiescent current ( $I_{\mathrm {Q}}$ ). In addition, it provides a power-supply rejection (PSR) more than 10 dB across all frequencies, effectively mitigating PSIJ caused by a noisy and complex PDN.