电压降
频率补偿
沉降时间
低压差调节器
电容器
信号边缘
控制理论(社会学)
时钟频率
同步电路
电压调节器
CMOS芯片
跌落电压
计算机科学
电子工程
电压
工程类
电气工程
时钟信号
电子线路
数字信号处理
控制工程
模拟信号
人工智能
阶跃响应
控制(管理)
作者
Dong-Jick Min,Jun-Gi Lee,Kunhee Cho,Jae Hoon Shim
标识
DOI:10.1109/iscas46773.2023.10182029
摘要
A typical digital low-dropout regulator (DLDO) that is clocked with a fixed frequency suffers from the trade-offs between power, speed, and stability. This paper proposes a DLDO that achieves both fast settling and low power consumption without limit-cycle oscillation (LCO) by adaptively changing the clock frequency and eventually turning off the clock in the steady state. The proposed LDO also features an inverter-based droop-compensation circuit for output-capacitor-free operation. The proposed LDO designed in a 28-nm CMOS process achieves a 70-ns settling time and a 137-mV droop voltage for the 400-mA load current transition with a 2.6-ns edge time, which translates to the figure of merit of 4.8 fs.
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