Proposal of Scalable Vector Extension for Embedded RISC-V Soft-Core Processor

Recently, the opportunity to use FPGA in the field of embedded computer system has increased. The cost for development of system using FPGA is quite high. Therefore, to easily develop the embedded system using FPGA, the development cost should be reduced, and it can be reduced by limiting the development of the dedicated circuit to the truly required part of the system and by using soft-core processor. If the performance of the soft-core processor improves, the development cost can be suppressed, since we can expect that the amount of the dedicated circuit can be reduced. Furthermore, even in the field of embedded system, the opportunity for data parallel processing such as image processing is increasing. We consider that it is important merit of soft-core processor with SIMD extension that the computation performance can be optimized to the system by changing the number of parallel computing units according to the application. However, when optimizing the performance of soft-core processor, it is an obstacle that the software for soft-core processor needs to be changed every time we change the number of computing units. Thus, vector processing facility should provide the scalability that means the number of computing units can be changed without changing the program code. In this paper, we propose a scalable vector extension for RISC-V ISA and its programming method.