无杂散动态范围
逐次逼近ADC
有效位数
总谐波失真
电容器
转换器
CMOS芯片
动态范围
电子工程
塑造
计算机科学
物理
电气工程
工程类
电压
作者
Yuan Ma,Xuecheng Wang,Milin Zhang
标识
DOI:10.1109/icicm54364.2021.9660262
摘要
This paper presents a differential 62. 5kS/s, 300nW,8bit successive approximation register (SAR) analog-to-digital converters (ADC) in 40nm CMOS technology occupying a silicon area of $0.005\mathrm{m}\mathrm{m}^{2}$. An algorithm that calculates the impact of capacitor mismatch errors and parasitic effects on performance for multi-structure comparison and area optimization has been proposed. The measured FOM of the proposed ADC is 14.9fJ/c-s at 62. 5kS/s with Effective number of bits (ENoB) of 8. 3bits, spurious free dynamic range (SFDR) of 63.34 dB and total harmonic distortion (THD) of 60.9 dB are achieved.
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