A 12 bit 2.9 GS/s DAC With IM3 $ ≪ -$60 dBc Beyond 1 GHz in 65 nm CMOS

A 12 bit 2.9 GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an $IM3 ≪ -60~{\hbox {dBc}}$ beyond 1 GHz while driving a 50 $\Omega $ load with an output swing of 2.5 $V_{\rm ppd}$ and dissipating a power of 188 mW. The SFDR measured at 2.9$~$ GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at high-frequencies, compared to previously published results, is mainly obtained by adding local cascodes on top of the current-switches with "always-ON" biasing.