NMOS逻辑
CMOS芯片
频道(广播)
缩放比例
材料科学
光电子学
物理
晶体管
计算机科学
电气工程
电信
工程类
数学
量子力学
几何学
电压
作者
Ang‐Sheng Chou,Ching-Hao Hsu,Yu‐Tung Lin,Goutham Arutchelvan,Edward Chen,Terry Y.T. Hung,Chen-Feng Hsu,Sui-An Chou,Tsung-En Lee,Oreste Madia,G. Doornbos,Yuan-Chun Su,Amin Azizi,D. Mahaveer Sathaiya,Jin Cai,Jer-Fu Wang,Yun-Yan Chung,Wen-Chia Wu,Katie Neilson,Wei‐Sheng Yun
出处
期刊:
日期:2023-12-09
卷期号:: 1-4
被引量:18
标识
DOI:10.1109/iedm45741.2023.10413779
摘要
Two-dimensional (2D) transition metal dichalcogenide (TMD) materials are regarded as promising channel candidates for extreme contacted gate pitch (CGP) scaling. However, basic demonstration of the modules required to build logic devices is limited. For the first time, we demonstrate comparable n-type and p-type high-performance on 2D transistors. Translation to 300 mm wafer processing is tested by die-by-die transfer of the 2D material. The 300 mm fabrication preserves a relatively high mobility of 30 cm 2 /V•s. We demonstrate scaling of nMOS contact length (L C ) to 12 nm and top gate length (L G ) to 10 nm. Devices maintain high current density at short L C as well as in top-gate only operation.
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