Review on BIST architectures of DRAMs

As the technology continues to grow, different kinds of DRAMs and their testing architectures are being developed. This paper focuses on the comparison of various BIST architectures of DRAM in the recent times. In this paper, an In-DRAM built-in self-test (BIST) mechanism for the bit cell failures caused by external environment is compared with itself using two different test algorithms for better performance. It is also compared high bandwidth memory (HBM) BIST, HBM 2 Extension (HBM2E) BIST and channel-sharable BIST architecture for the demand of high bandwidth. The different characteristics of the DRAM BISTs' such as area overhead, test time reduction, test patterns, modes, operating voltages, temperatures and faults detected using these BISTS have been compared in this paper as follows.