Boosting the Accuracy of SRAM-Based in-Memory Architectures Via Maximum Likelihood-Based Error Compensation Method

SRAM-based analog in-memory computing (IMC) architectures have demonstrated high energy efficiency and compute density over digital accelerators for machine learning. However, their compute SNR and achievable dot product (DP) dimension are limited by the analog nature of computations. We present a Maximum Likelihood (ML)-based statistical Error Compensation (MLEC) method to enhance the accuracy of binary DPs in a 6T SRAM-based IMC. MLEC leverages the IMC architecture to extract multiple observations and implements an approximate ML detection rule. Employing simulations in a 28nm CMOS and behavioral modeling, we show that MLEC enhances the compute SNR by 5dB-to-30dB over a conventional IMC with an energy overhead ranging from 10%-to-30% for DP dimensions of 64-to-256.