材料科学
MOSFET
快速切换
切换时间
电压
功率MOSFET
光电子学
功率半导体器件
电气工程
碳化硅
击穿电压
随时间变化的栅氧化层击穿
阈值电压
阻塞(统计)
高压
电容感应
功率(物理)
脉冲功率
栅极电压
半导体器件
雪崩击穿
逻辑门
电子工程
门驱动器
寄生提取
工程物理
开关电源
和大门
宽禁带半导体
寄生元件
作者
Nianzun Qi,Masaki Takahashi,Morten Rahr Nielsen,Zhixing Yan,Gao Liu,Stefan Meyer,Hongbo Zhao,Asger Bjørn Jørgensen,Stig Munk‐Nielsen
标识
DOI:10.1109/ecce58356.2025.11259922
摘要
As the industry shifts toward higher voltage classes of semiconductor devices such as 6.5 kV and 10 kV SiC MOS-FETs, these devices exhibit intrinsically faster switching speeds. This requires a re-evaluation of the design regime on parasitic optimization priority in power module design, which previously have been primarily focused at lowering the parasitic inductance. This paper presents a theoretical analysis of switching speed changes with breakdown voltage based on device cell structure, and the experimental comparison of the switching speed (dv / dt and di/dt) of MV SiC MOSFETs with blocking voltages of 3.3 kV, 6.5 kV, and 10 kV. The results reveal that higher-voltage SiC MOSFETs experience higher dv/dt with same gate resistance, indicating that SiC MOSFETs are more sensitive to parasitic capacitive couplings as breakdown voltage increasing. While the di/dt of three chosen SiC MOSFETs overlay with each other with same gate resistance. These findings provide quantitative insights into breakdown-voltage-dependent switching speed, serving as a practical guideline for future MV SiC MOSFET power modules featuring high-voltage and high-current capability.
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