Failure mechanism of silicon germanium (SiGe) technology on 90nm PMOS

This research was conducted to study the effect of strain silicon on 90nm PMOS using graded silicon germanium (SiGe). By introducing graded silicon germanium layer under the gate oxide, the performance of conventional 90nm PMOS and 90nm PMOS with silicon germanium layer was compared. The analysis focused on Id-Vg, Id-Vd characteristic, and hole mobility changes. TCAD SILVACO simulator was used to simulate the device process and electrical characteristic of 90nm PMOS structure. The final result shows that, biaxial strain silicon decreased the drive current on 90nm PMOS structure to 35% observed from test gate voltage of − 0.5V. The results were obtained from ATHENA and ATLAS simulator.