A 12b 1GS/s SAR-Assisted Pipelined ADC with Gain-Error-Cancelled Dual-Path Amplifier and Partially Look-Ahead Parallel Quantization

This paper presents a 12b 1GS/s SAR-assisted pipelined ADC, featuring two key techniques for high speed and high resolution: gain-error-cancelled dual-path amplifier and partially look-ahead quantization. Fabricated in 28-nm CMOS, the prototype ADC achieves an SNDR above 60 dB and an SFDR above 72 dB at 1 GS/s across $-40^{\circ} \mathrm{C}$ to 125° C and with $\pm 10 \%$ supply voltage variation without background calibration. It consumes 9.63 mW, yielding an FoMw of $11.4 \text{fJ} /$ conv-step and FoMs of 167.5 dB.