Indium-capped Copper Pillar Flip-chip Scheme Compatible for 2.5D Superconducting Quantum Computing Architecture

High-density vertical interconnects are required for scalable superconducting quantum processors, where both mechanical reliability and cryogenic electrical behavior must be considered. Electroplating provides an efficient route for wafer-level In deposition, but the Cu seed layer or redistribution layer used for current delivery may leave a normal-metal contribution in the low-temperature signal path. In this work, an In-capped Cu pillar and redistribution layer (RDL) flip-chip scheme is demonstrated for 2.5D superconducting quantum integration. The electroplated Cu pillar is used as the mechanical support to define the interconnect height, while a wafer-level electroplated In layer covers the Cu pillar and the underlying RDL to form an In-covered current route around the Cu-based structure. Daisy chain test vehicles with 116 and 960 bonding pairs are fabricated and bonded at room temperature. Cross-sectional FIB-prepared SEM images and EDS mapping show continuous In coverage over the Cu pillar and RDL region, with no obvious voids, cracks and interfacial delamination in the inspected section. X-ray inspection shows good bump alignment without obvious bridging, shorting between adjacent bumps, or gross misalignment. Electrical measurements show a linear current-voltage response at room temperature and a clear resistance drop near 3 K during cooling, close to the superconducting transition of bulk In. These results suggest that the proposed In-capped Cu pillar and RDL architecture combines the process compatibility of Cu electroplating with the cryogenic advantage of In, providing a feasible interconnection approach for 2.5D superconducting quantum packaging.