A Fully Reconfigurable Low Offset Asymmetric Sense Amplifier Implementing Multiple Logic Gates for In-Memory Computing

This work proposes a low offset asymmetric sense amplifier (LO-ASA) to perform in-memory boolean logic computations. The design uses a single capacitor to reduce the offset introduced by the input transistors of the sense amplifier. The resultant low offset sense amplifier becomes asymmetric and helps to implement multiple logic gates like$NOR$,$OR$,$AND$,$NAND$,$XNOR$and$XOR$. The proposed$128\times 128$SRAM architecture requires only one LO-ASA per column to implement the desired logic gates using a logic selection circuit. The circuit is designed and simulated in UMC 65 nm CMOS technology using a 1.2 V power supply. The worst case standard deviation of offset observed for the conventional current latch sense amplifier and the proposed LO-ASA are 12.2 mV and 9.1 mV, respectively, evaluated for 1000 Monte Carlo runs at$3\sigma $deviation. The proposed sense amplifier results in a yield of 99.7%, 100%, and 99.6%, respectively corresponding to boolean logic$NOR/OR$,$AND/NAND$, and$XNOR/XOR$at a nominal temperature of 27°C. In addition, the worst-case power delay product of 5.2 fJ, 9.5 fJ, and 26 fJ is achieved for$NOR$,$AND$, and$XNOR$gates, respectively.