This paper presents an energy-efficient True Random Number Generator (TRNG) architecture, referred to as the Modified Chaotic Logistic Map with Braided XOR Network (MCLM-BXN). The proposed system exploits the diffusion of noise from two 4-bit tapped Ring Oscillators (ROs), which serve as the entropy sources. These jitter-induced signals are injected into a Modified Chaotic Logistic Map (MCLM) module to enhance the generated randomness. To further improve entropy and reduce statistical correlation, an 8-input, 1-output Braided XOR Network (BXN) module is employed as a post-processing stage. The MCLM-BXN architecture is implemented on the INTEL 5CGXFC9D6F27C7 Cyclone V GT FPGA chip. Supported by the Data Storage and Transmitting Unit-300 (DSTU-300), the TRNG achieves a throughput of 300 Mbps. Experimental evaluations confirm high entropy levels, recording approximately 7.998893 bits/byte using the AIS-31 T8 test and 7.963032 bits/byte according to the NIST SP800-90B test. Furthermore, the proposed TRNG passes the full NIST SP800-22 statistical test suite, validating its effectiveness and suitability for cryptographic applications.