Modeling of silicon nitride chemical vapor deposition in high aspect ratio nano-scale substrate features

Three-dimensional (3D) architectures have become main stream for the advanced node logic and memory devices, such as the gate-all-around field effect transistors (GAAFET) and 3D dynamic random access memory (3D DRAM). These devices feature with stacked structure offers higher integration, better device performance and lower power consumption. However, the manufacturing of such devices needs high aspect ratio (AR) feature processing which brings challenges to conventional thin film deposition process such as chemical vapor deposition (CVD). SiN is a common barrier and spacer material and usually grown by CVD with a gas mixture of SiH₄/NH₃/N₂. In this work, we conduct simulations of SiN CVD process in deep trenches to investigate the thin film step coverage dependence on process conditions and AR. We adopt the reaction-diffusion theory to develop the surface growth model of SiN deposition and set a few semi-empirical mechanism parameters to calibrate the model with experimental results. Simulation results show that in the substrate trench with 50nm open CD and AR of 5, the film deposition step coverage becomes better as the fluxes of neutrals increases, corresponding to lager f_neu value. Simulations also suggest that with trench depth fixed at 250nm, as the AR of the trench increases, the overall deposition rate in the trench decreases. As the AR increases, the density of the reactant species such as radicals and ions decrease and the diffusion-limited phenomenon appear, which further reduces the reaction rate at the bottom of the trench.