In-Depth Timing Characterization of the Adiabatic Quantum-Flux-Parametron Logic Gate

CMOS circuits are facing the physical limitations of miniaturization and increasing leakage current. We need new circuit technologies that can operate with low power consumption instead of CMOS circuits to support the growing demand for information and communications technology (ICT). Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family and can operate at 5–10 GHz with extremely low switching energy. We use digital simulation models specified in Verilog or SystemVerilog to design large-scale circuits using AQFP logic gates. Previous work on digital modeling used unconventional timing checks and the timing characteristics of the AQFP logic gates were simplified. The intrinsic delays of the AQFP logic gate, such as propagation and reset delay, were not characterized in depth. To design large-scale circuits with GHz operating frequencies, a more in-depth timing characterization and a more accurate timing model with industry-standard timing checks are needed. In this study, we investigate the appropriate timing definitions and new methods to evaluate the timing parameters of the AQFP logic gates for digital simulation. We observe new timing effects in the AQFP and determine how to properly consider them during characterization. We also consider a few approaches on how to realize the timing model and identify a candidate implementation.