Detection of crystalline defects in Si/SiGe superlattices towards 3D-DRAM applications

Si/SiGe heterostructures are gaining traction as a starting template in applications such as Gate-All-Around Field-Effect Transistor (GAAFET), complementary FET (CFET), and 3-dimensional dynamic random access memory (3D-DRAM), where the SiGe alloy plays the role of sacrificial material for channel release. However, the formation of crystalline defects (e.g. crosshatch) in the epitaxially grown layers plays a critical part in determining the overall device performance. As such, it is key to be able to control the defectivity level using large surface area inspection techniques. The challenge of such inspection is that it must combine a high enough throughput to detect low-density defects together with sensitivity to nanometer size defects. In addition, the technique should also be able to distinguish these elongated one-dimensional crystalline defects from other types of defects. In this study, we investigate the impact of the number of Si/SiGe bilayers on the crystal defect distribution utilizing a combined approach of optical inspection and extensive e-beam review for both qualitative and quantitative defect characterization. In-line optical inspection techniques revealed that the crosshatch density and distribution varied significantly with the number of Si/SiGe bilayers. These observations were then confirmed by high-resolution e-beam review coupled with image analysis and signal processing to enable crosshatch quantification. Our approach considers an initial investigation on thin Si/SiGe bilayers (up to ~5x bilayers) and is further extended to thick stacks (up to 60x bilayers) to evaluate the capability of optical inspection as the high-throughput reference technique. In conclusion, this study aims to develop a methodology to investigate the crosshatch density in Si/SiGe superlattices, using optical inspection and e-beam review as main characterization tools. These techniques offer valuable insights in terms of defect distribution at the wafer level for the design and fabrication of next-generation semiconductor devices.