Implementation of a SerDes-Based Timing Generator and Formatter

In integrated circuit testing, the diversity and precision of digital test pattern are critical to ensuring the yield of the device under test (DUT). As the integration level of DUTs continues to increase, the digital test module, as a key component of automatic test equipment (ATE), is facing increasingly stringent requirements in terms of pattern formats, output data rates, and edge precision. In this context, this paper presents a Timing Generator and Formatter. As a core component of digital testing functionality, it supports digital pattern generation at speeds up to 3.2 Gbps and accommodates multiple formats, including Return-to-Zero (RZ), Return-to-One (RO), Surround By Complement (SBC), and others.