Bias-stress-induced stretched-exponential time dependence of charge injection and trapping in amorphous thin-film transistors

The threshold voltage instabilities in nitride/oxide dual gate dielectric hydrogenated amorphous silicon (a-Si:H) thin-film transistors are investigated as a function of stress time, stress temperature, and stress bias. The obtained results are explained with a multiple trapping model rather than weak bond breaking model. In our model, the injected carriers from the a-Si:H channel first thermalize in a broad distribution of localized band-tail states located at the a-Si:H/aSiNx:H interface and in the a-SiNx:H transitional layer close to the interface, then move to deeper energies in amorphous silicon nitride at longer stress times, larger stress electric fields, or higher stress temperatures. The obtained bias-stress-temperature induced threshold voltage shifts are accurately modeled with a stretched-exponential stress time dependence where the stretched-exponent β cannot be related to the β=TST/T0 but rather to β≂TST/T0*−β0 for TST≤80 °C; for TST≥80 °C, the β is stress temperature independent. We have also found that β is stress gate bias independent.