材料科学
原子层沉积
沟槽
与非门
光电子学
蚀刻(微加工)
薄膜
制作
进程窗口
无定形固体
图层(电子)
纳米技术
电子工程
逻辑门
病理
有机化学
化学
工程类
平版印刷术
替代医学
医学
作者
Yingjie 英杰 Fan 樊,Yaming Wang,Haiteng Huang,Jingjing Zhang,Lihui Yu,Jingquan Guo,Qiutong Zhao,Shujun Zhang,Z. Chen,Shujun Ye
出处
期刊:Nanotechnology
[IOP Publishing]
日期:2025-07-23
卷期号:36 (31): 315301-315301
标识
DOI:10.1088/1361-6528/adf33e
摘要
Ultimate-vertical-gate-all-around (UVGAA) MOSFET represent an advanced evolution of VGAA architectures, featuring source-drain symmetry enabled by simultaneous formation of both terminals. Derived from the fabrication methods of three dimensional (3D) NAND flash memory, UVGAA MOSFET offer potential for vertically stacked logic circuits. However, their implementation demands ultra-thin sacrificial Si3N4layers and higher lateral-high-aspect-ratio (LHAR) trench structures compared to 3D NAND flash memory. In this study, 20 nm thick multilayer LHAR trench structures with aspect ratio up to 30 were successfully fabricated via a combined dry and wet etching approach applied to SiO2-Si3N4-SiO2multilayer stacks. Hafnium dioxide (HfO2) thin films were subsequently deposited within these confined geometries and on planar silicon surfaces using atomic layer deposition. By systematically optimizing key process parameters: precursor pulse time and purge duration-optimal conditions for uniform and conformal film growth were established. The comprehensive deposition behavior of HfO2films in different geometric structures has been qualitatively analyzed using the molecular diffusion theory and the surface adsorption kinetics model. Resulting HfO2films exhibited predominantly amorphous structure, ultra-low surface roughness, and excellent electrical properties. This study establishes a theoretical framework and process foundation for the miniaturization and performance optimization of next-generation 3D integrated circuits.
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