管道（软件）
CMOS芯片
放大器
电容器
计算机科学
电子工程
电气工程
总谐波失真
均衡（音频）
开关电容器
工程类
频道（广播）
电压
程序设计语言
作者
Jiangfeng Wu,Acer Chou,Cheng-Hsun Yang,Yen Ding,Yen-Jen Ko,Sha-Ting Lin,Wenbo Liu,Chi-Ming Hsiao,Ming-Hung Hsieh,Chun-Cheng Huang,Juo-Jung Hung,Kwang Young Kim,M.Q. Le,Tianwei Li,Wei-Ta Shih,Ayaskant Shrivastava,Yau-Cheng Yang,Chunying Chen,Hung-Sen Huang
摘要
A 5.4GS/s 12b 2-way interleaved pipeline ADC is presented. To achieve high speed, a complementary switched-capacitor amplifier is proposed, along with ping-pong amplifier sharing and digital MDAC equalization. The ADC achieves 61dB SNR and 57dB THD up to 2.6GHz input frequency at 5.4GS/s, consumes 500mW and occupies 0.4mm2 area in 28nm CMOS.
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