抛光
薄脆饼
平坦度(宇宙学)
材料科学
研磨
研磨
蚀刻(微加工)
化学机械平面化
复合材料
冶金
光电子学
工程制图
图层(电子)
工程类
物理
量子力学
宇宙学
作者
Genghang Zhong,Yongduo Ning,Qing Zhou,Yongzhi Bian,Xin Wang,Qian Xiang,Lei Wang,Erjing Zhao
标识
DOI:10.1016/j.mssp.2017.05.031
摘要
Abstract The preparation of semiconductor silicon polished wafer is a multi-stage manufacturing process. This paper analyzed the influence of polished wafers’ SFQR (Site flatness front least square range) values with different pre-polishing process. In this study, the pre-polishing processes included dual-side lapping & etching, dual-side grinding and back-side polishing. Among them, the etching process was divided into caustic etching and acid etching with different removal amount and different rotation speed. The experimental results show that different pre-polishing processes have significant effects on SFQR values of polished wafers. Caustic etching, dual-side grinding and back-side polishing are more suitable for polished wafer's SFQR, while the center area of acid etching wafers show worse polished wafer's SFQR due to the etching mechanism.
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