An Active Gate Driver Control Scheme for Steady-State Current Balancing of Paralleled SiC MOSFETs

Silicon carbide (SiC) modules are increasingly adopted in high power applications, where paralleling multiple modules is a common practice to achieve high current carrying capability. This, however, leads to unbalanced current sharing among the paralleled modules. Active gate driver (AGD) can regulate switching behavior of MOSFETs, which has been widely studied to solve the unbalanced current issue among paralleled SiC MOSFETs. An AGD control method targeted at mitigating steady unbalanced current among paralleled SiC MOSFETs is proposed in this brief. The equivalent on-state drain-to-source resistance of paralleled MOSFETs is regulated by applying pulse width modulation (PWM) between two voltage rails in the AGD to compensate parameter mismatches causing steady-state unbalanced current. The proposed AGD can also eliminate the transient unbalanced current by manipulating the delay between the devices in parallel. Comprehensive double pulse tests were conducted to validate the effectiveness of the proposed method. Extensive loss analysis has been performed to highlight the ability of the proposed AGD to achieve evenly loss distribution among modules under different case temperatures and DC bus voltages. The proposed AGD current balancing method is straightforward to implement but was proven to effectively address the current issues among the paralleled SiC modules.