A Design of Phase Shifting Phase Locked Loop with Dual Loop Structure for Beamforming Application

This paper presents a structure of Phase-Locked Loop (PLL) that can shift phase by itself. The frequency of the reference clock is 50MHz, and the target frequencies are 5.8 GHz and 4.8 GHz. The PLL structure in this paper has one more Phase-Frequency-Detector (PFD) and one more charge pump. The key idea is to apply two divider output signals with constant delay to each PFD and Charge Pump, then the phase of the output signal of Voltage-Controlled-Oscillator (VCO) is shifted depending on the current of two charge pumps. In this paper, the circuit was designed using a 130nm CMOS process. The phase shifting resolution of the designed PLL is 5.625 degrees.