The circuit design and optimization of quantum multiplier and divider

A fault-tolerant circuit is required for robust quantum computing in the presence of noise. Clifford + T circuits are widely used in fault-tolerant implementations. As a result, reducing T-depth, T-count, and circuit width has emerged as important optimization goals. A measure-and-fixup approach yields the best T-count for arithmetic operations, but it requires quantum measurements. This paper proposes approximate Toffoli, TR, Peres, and Fredkin gates with optimized T-depth and T-count. Following that, we implement basic arithmetic operations such as quantum modular adder and subtracter using approximate gates that do not require quantum measurements. Then, taking into account the circuit width, T-depth, and T-count, we design and optimize the circuits of two multipliers and a divider. According to the comparative analysis, the proposed multiplier and divider circuits have lower circuit width, T-depth, and T-count than the current works that do not use the measure-and-fixup approach. Significantly, the proposed second multiplier produces approximately 77% T-depth, 60% T-count, and 25% width reductions when compared to the existing multipliers without quantum measurements.